Meyers, T.T.MeyersVidor, F.F.F.F.VidorHilleringmann, UlrichUlrichHilleringmann2022-03-132022-03-132016https://publica.fraunhofer.de/handle/publica/395460In order to improve the cut-off frequency in digital circuits a reduction of parasitic capacitances is requested. In this article we present a maskless integration process to reduce crosstalk by patterning the dielectric layer in the field region of the transistor template. Additionally, a method for structuring the semiconducting layer in the field region by lift-off technique is shown. All process steps are limited to a maximum temperature of 115°C aiming at the compatibility with flexible substrates.enconference paper