Clausner, AndréAndréClausnerSchlipf, SimonSimonSchlipfKurz, G.G.KurzOtto, M.M.OttoPaul, J.J.PaulGiering, Kay-UweKay-UweGieringWarmuth, JensJensWarmuthLange, AndréAndréLangeJancke, RolandRolandJanckeAal, A.A.AalRosenkranz, RüdigerRüdigerRosenkranzGall, MartinMartinGallZschech, EhrenfriedEhrenfriedZschech2022-03-132022-03-132018https://publica.fraunhofer.de/handle/publica/40099010.1109/IRPS.2018.835360728 nm high-k metal gate CMOS SRAM circuits were subjected to controlled mechanical load by nanoindentation. A thinning procedure down to about 35 mum of remaining Si enables high stress fields in the vicinity of operational SRAM cells which were embedded in a flip chip package and subjected to loads from the Si backside. It was found that the loading leads to an increase of the bit cell fail probability around the nanoindentation point. The loading effects are reversible, i.e. failures are completely released upon load relieve. The results attained here provide a quantitative estimate about the influence of package-related stress on performance and reliability of microelectronic products during field operation, shedding light on CPI-and CBI-effects.enCMOS memory circuitsNanoindentationsiliconSRAM chips621620666004conference paper