Evaluating an Open-Source Hardware Approach from HDL to GDS for a Security Chip Design - a Review of the Final Stage of Project HEP

Henkes, TimTimHenkesReith, SteffenSteffenReithStöttinger, MarcMarcStöttingerHerfurth, NorbertNorbertHerfurthPanic, GoranGoranPanicWälde, JulianJulianWäldeBuschkowski, FabianFabianBuschkowskiSasdrich, PascalPascalSasdrichLüth, ChristophChristophLüthFunck, MilanMilanFunckKiyan, TubaTubaKiyanWeber, ArndArndWeberBoeck, DetlefDetlefBoeckRathfelder, RenéRenéRathfelderGrawunder, TorstenTorstenGrawunder2024-06-272024-06-272024https://publica.fraunhofer.de/handle/publica/470489The project "Hardening the value chain through open-source, trustworthy EDA tools and processors (HEP)" uses open-source, free components and tools for the production of a prototypical security chip. A design flow using only free and open tools from the abstract description in SpinalHDL via OpenROAD down to the GDS-file for tape-out has been established, and first ASICs produced at IHP. The prototypical hardware security module (HSM) produced in this way provides, among other things, a processor based on VexRiscv, a cryptographic accelerator and masking of cryptographic keys. The open development tools used in the process were integrated into a common environment and expanded to include missing functionality. Subsequently, the whole tool chain and its peripherals are wrapped into a new Nyx container. The easy accessibility of the used process significantly reduces the learning curve for chip design. Additionally, we provide tools for formal verification and masking against side-channel attacks in our design flow. Interest in the results of project HEP has been shown in publications in which industrial partners participated, such as Elektrobit, Hensoldt Cyber, IAV, Secure-IC and Swissbit Germany.enopen-sourcehardwareside-channelEvaluating an Open-Source Hardware Approach from HDL to GDS for a Security Chip Design - a Review of the Final Stage of Project HEPconference paper