Lin, K.-L.K.-L.LinBoom, T. van denT. van denBoomStevanovic, N.N.StevanovicDriesen, J.J.DriesenHammerschmidt, D.D.HammerschmidtHosticka, B.J.B.J.Hosticka2022-03-092022-03-091999https://publica.fraunhofer.de/handle/publica/332516The design techniques for analog-to-digital converters (ADCs) require careful optimization in order to minimize the amount of hardware required and enable economical monolithic integration. A basic architectural design guide dedicated to folding and interpolating ADCs is outlined and described. A case study for a 10bit ADC is treated under consideration of different folding and interpolating factors. The trade-off between chip area, power dissipation, and ADC performance is characterized according to the diverse design variables.enanalogue-digital conversioncomparatorfolderfolding/InterpolationInterpolationKonverterleistungsarmes Bauelementlow power621conference paper