Fazzi, A.A.FazziMagagni, L.L.MagagniMirandola, M.M.MirandolaCanegallo, R.R.CanegalloSchmitz, S.S.SchmitzGuerrieri, R.R.Guerrieri2022-03-102022-03-102005https://publica.fraunhofer.de/handle/publica/35042910.1109/CICC.2005.1568618This paper presents a synchronous 3D interconnection based on capacitive coupling. The designed link presents a power consumption of 0.128mW/pin@975Mbps/ pin, overcoming standard I/O pads performance of two orders of magnitude. High bit-rate, reduced power consumption and electrode area down to 8×8m2 enable the implementation of highly parallel pipelined interfaces for inter-chip communication, with an aggregate consumption of about 0.14mW/Gbps. ©2005 IEEE.en621conference paper