Burenkov, A.A.BurenkovLorenz, J.J.Lorenz2022-03-102022-03-102004https://publica.fraunhofer.de/handle/publica/345356Coupled three-dimensional process and device simulations have been applied to study effects limiting the performance of FinFETs, a novel CMOS transistors suggested to overcome the limitations of conventional CMOS for gate lengths at 50 nm and below.enprocess simulationdevice simulationdevice performancedevice scalabilityspread of process result6706205303D simulation of process effects limiting FinFET performance and scalability3D-Simulation von prozessierungsrelevanten Effekten, welche die Leistungsfähigkeit und Miniaturisierung von FinFETs beschränkenconference paper