Donath, U.U.DonathSchwarz, P.P.Schwarz2022-03-032022-03-032002https://publica.fraunhofer.de/handle/publica/20269210.1524/auto.2002.50.9.a21VHDL is a standardised hardware description language used in the design of digital systems. The first part of the paper presents the basic constructions of the language and illustrates their applications. The following parts describe application aspects for an automation systems. In addition, AMS extension of VHDL for modelling continuous systems is outlined.ensystem viewlanguage constructVHDLhardware description languagedigital system designcontinuous system621004006629journal article