Schönherr, J.J.SchönherrFreibothe, M.M.FreibotheStraube, B.B.StraubeBormann, J.J.Bormann2022-03-102022-03-102008https://publica.fraunhofer.de/handle/publica/35875110.1016/j.tcs.2008.03.032In this article, a verification methodology for mixed-signal Circuits is presented that can easily be integrated into industrial design flows. The proposed verification methodology is based on formal verification methods. A VHDL behavioral description of a mixed-signal circuit is transformed into a discrete model and then verified using well-established tools from formal digital verification. Using the presented methodology, a much higher coverage of the functionality of a mixed-signal circuit can be achieved than with simulation based verification methods. The approach has already been successfully applied to industrial mixed-signal circuits.en621004conference paper