Vogelsang, FlorianFlorianVogelsangBredendiek, ChristianChristianBredendiekSchöpfel, JanJanSchöpfelRücker, HolgerHolgerRückerPohl, NilsNilsPohl2023-07-122023-07-122022https://publica.fraunhofer.de/handle/publica/44551310.1109/BCICTS53451.2022.100517042-s2.0-85150073451This work presents a static divide-by-16 in a 130-nm SiGe-BiCMOS technology, aiming to demonstrate the technologies' potential. A bias network followed by four divide-by-2 stages and an output buffer is designed. The DC power consumption of the first divider stage and the four divider flip flops in static current mode logic (CML) with buffer is 134.3 mW and 396 mW, respectively. The maximum input frequency of the divider is 163 GHz. The corresponding necessary input power at the divider's bias network is 4.39 dBm. The observed self-oscillating frequency is 110.56 GHz, while the output power at the by-16 output of the divider is around -9 dBm. Moreover, a special focus is set on the accuracy of divider simulations and the influence of parasitic elements compared to measurement results.enfrequency synthesismm-WaveSiGe BiCMOSstatic frequency dividerconference paper