Awny, A.A.AwnyNagulapalli, R.R.NagulapalliKroh, M.M.KrohHoffmann, J.J.HoffmannRunge, P.P.RungeMicusik, D.D.MicusikFischer, G.G.FischerUlusoy, A.C.A.C.UlusoyKo, M.M.KoKissinger, D.D.Kissinger2022-03-052022-03-052018https://publica.fraunhofer.de/handle/publica/25023710.1109/TMTT.2017.2752170This paper presents the design and measurements of a 32-Gb/s differential-input differential-output transimpedance amplifier (TIA) employed in dual polarization integrated coherent receivers for 100-Gb Ethernet. A circuit technique is shown that uses a replica TIA to stabilize the operating point of the two shunt-feedback input stages as well as to cancel the dc part of the two complementary input currents and balances their offset. The TIA can be operated in two modes, an automatic gain control mode to retain a good total harmonic distortion (THD) over a wide dynamic range and a manual gain control mode. Electrical as well as optical-electrical characterization of the TIA are presented. It achieves a maximum differential transimpedance of 74 dBO, 33 GHz of 3-dB bandwidth, 12.2 pA/SRHz of average input-referred noise current density with the photodiode, 900 mVpp of maximum differential output swing, less than 1% of THD for 600 mVpp differential output swing, and 500 mApp differential input current. The linearity of the TIA is furthermore demonstrated with PAM4 measurements at 25 Gbaud. The dual TIA chip is fabricated in a 0.13-mm SiGe:C BiCMOS technology, dissipates 436 mW of power and occupies 2 mm² of area.en621journal article