Porteau, M.-L.M.-L.PorteauGharbi, A.A.GharbiBrianceau, P.P.BrianceauDallery, J.-A.J.-A.DalleryLaulagnet, F.F.LaulagnetRademaker, G.G.RademakerTiron, R.R.TironEngelmann, Hans-JürgenHans-JürgenEngelmannBorany, Johannes vonJohannes vonBoranyHeinig, Karl-HeinzKarl-HeinzHeinigRommel, MathiasMathiasRommelBaier, LeanderLeanderBaier2022-03-062022-03-062020https://publica.fraunhofer.de/handle/publica/26406810.1016/j.mne.2020.100074SETs (Single-Electron-Transistors) arouse growing interest for their very low energy consumption. For future industrialization, it is crucial to show a CMOS-compatible fabrication of SETs, and a key prerequisite is the patterning of sub-20 nm Si Nano-Pillars (NP) with an embedded thin SiO2 layer. In this work, we report the patterning of such multi-layer isolated NP with e-beam lithography combined with a Reactive Ion Etching (RIE) process. The Critical Dimension (CD) uniformity and the robustness of the Process of Reference are evaluated. Characterization methods, either by CD-SEM for the CD, or by TEM cross-section for the NP profile, are compared and discussed.ensingle-electron-transistormultilayer nanopillarsSi nanodotse-beam lithographyICP-RIEEFTEM670620530journal article