Barnasconi, MartinMartinBarnasconiPêcheux, FrançoisFrançoisPêcheuxVörtler, ThiloThiloVörtler2022-03-122022-03-122014https://publica.fraunhofer.de/handle/publica/384160This paper introduces the Universal Verification Methodology (UVM) using SystemC and C++ (UVM-SystemC), to advance system-level verification practices. UVM-SystemC enables the creation of a structured, modular, configurable and reusable test bench environment. Unlike other initiatives to create UVM in SystemC, the presented proof-of-concept class library uses identical constructs as defined in the UVM standard for test and sequence creation, verification component and test bench configuration and execution by means of simulation. Users familiar with either SystemC and/or with UVM will immediately feel comfortable to start using UVM-SystemC right away. The Universal Verification Methodology becomes universal, at last.enElectronic System Level (ESL)Hardware-in-the-Loop (HiL)Rapid Control Prototyping (RCP)SystemCSystemC Verification (SCV)Transaction Level Modeling (TLM)Universal Verification Methodology (UVM)621004conference paper