Sk, Masud RanaMasud RanaSkThunder, SunandaSunandaThunderMüller, FranzFranzMüllerLaleni, NelliNelliLaleniRaffel, YannickYannickRaffelLederer, MaximilianMaximilianLedererPirro, LucaLucaPirroChohan, TalhaTalhaChohanHsuen, Jing HuaJing HuaHsuenWu, Tian LiTian LiWuSeidel, KonradKonradSeidelKämpfe, ThomasThomasKämpfeDe, SouravSouravDeChakrabarti, BhaswarBhaswarChakrabarti2023-09-262023-09-262023https://publica.fraunhofer.de/handle/publica/45097510.1109/TNANO.2023.32950932-s2.0-85164803418This letter proposes a memory cell, denoted by 1F-1 T, consisting of a ferroelectric field-effect transistor (FeFET) cascaded with another current-limiting transistor (T). The transistor reduces the impact of drain current ( Id ) variations by limiting the on-state current in FeFET. The experimental data from our 28 nm high-k-metal-gate (HKMG) based FeFET calibrates and simulates the memory arrays. The simulation indicates a significant improvement in bit-line (BL) current ( IBL ) variation and the accuracy of vector-matrix multiplication of the 1F-1 T memory array. The system-level in-memory computing simulation with 1F-1T synapses shows an inference accuracy of 97.6% for the MNIST hand-written digits with multi-layer perceptron (MLP) neural networks.en1/f noise1F-1TComputer architectureFeFETFeFETsLogic gatesMemory ArrayMicroprocessorsNeural networksTransistorsVector-matrix-multiplicationjournal article