Pai, A.P.A.P.PaiReiter, T.T.ReiterMaerz, M.M.Maerz2022-03-132022-03-132016https://publica.fraunhofer.de/handle/publica/400837In this paper, a new behavioural model is proposed for calculating power losses in power semiconductor switches. In contrast to models existing in literature which mostly model losses only in terms of Ic/f, Vdc and Tj, this paper also takes into account Rg and Vge which heavily affect the losses but are generally neglected. Moreover, the model also calculates losses as a function of the chip area per switch, which makes this model ideal for calculating the optimum chip area for a given application. The accuracy of this model is experimentally demonstrated on a HybridPACK Drive FS820R08A6P2 power module from Infineon, and the model is found to offer significantly better accuracy compared to the existing models.en670620530conference paper