Guo, RunningRunningGuoPechmann, StefanStefanPechmannHagelauer, AmelieAmelieHagelauer2025-01-022025-01-022024-08-11https://publica.fraunhofer.de/handle/publica/48096510.1109/MWSCAS60917.2024.10658733Resistive random-access memory (RRAM) devices have been frequently mentioned considering their robust performances. The conventional transistor one-memristor (1TIR) RRAM device becomes less competitive considering its multi- level operation. This paper introduces a two-transistor two- memristor (2T2 R) structure as well as a reading method for the configuration. The designed sense circuit based on a Strong-Arm latch codes 9 different states with 6 bits in 48ns and consumes a power of 7.6uW and it also demonstrates a tolerance to RRAM technologies and variations.en1TIR2T2RRRAM deviceStrong-Arm latchmulti-levelreading methodconference paper