Diaz-Madrid, J.-A.J.-A.Diaz-MadridNeubauer, H.H.NeubauerHauer, J.J.HauerDomenech-Asensi, G.G.Domenech-AsensiRuiz-Merino, R.R.Ruiz-Merino2022-03-112022-03-112009https://publica.fraunhofer.de/handle/publica/3624282-s2.0-70350045035High performance analog-to-digital converters (ADC) are essential elements for the development of high performance image sensors. These circuits need a big number of ADCs to reach the required resolution at a specified speed. Moreover, nowadays power dissipation has become a key performance to be considered in analog designs, specially in those developed for portable devices. Design of such circuits is a challenging task which requires a combination of the most advanced digital circuit, the analog expertise knowledge and an iterative design. Amplifier sharing has been a commonly used technique to reduce power dissipation in pipelined ADCs. In this paper we present a partial amplifier sharing topology of a 12 bit pipeline ADC, developed in 0.35µm CMOS process. Its performance is compared with a conventional amplifier scaling topology and with a fully amplifier sharing one.en621conference paper