Liebsch, W.W.LiebschBoettcher, K.K.Boettcher2022-03-082022-03-081992https://publica.fraunhofer.de/handle/publica/320618A parallel architecture and the implementation in CMOS technology is presented for high-speed forward and inverse two-dimensional discrete cosine transform. These circuits are applicable in advanced television and HDTV data reduction systems working at video sampling rates up to 80 MHz. The architecture utilizes the advantage of parallel and distributed arithmetic to achieve high-speed performance. An IDCT circuit is realized in 1.5 mu m CMOS technology as a full-custom VLSI component. It performs 720 million multiplications and 1280 million additions per second at nearly floating point precision for the 8 bit output values. The device demonstrates the transfer of a parallel and regular architecture for high-speed operation into a VLSI full-custom chip layout.encmos integrated circuitsdigital signal processing chipshigh definition televisionparallel architecturestransformsvideo signalsvlsivlsi implementationparallel architecturecmos technologytwo-dimensional discrete cosine transformHDTV data reduction systemsvideo sampling ratesdistributed arithmeticidct circuitfull-custom vlsihigh-speed operation1.5 micron621conference paper