20 Gbit/s 2 to 1 multiplexer using 0.3 mym gate length double pulse doped Quantum Well GaAs/AlGaAs transistors.

Nowotny, U.U.NowotnyLang, M.M.LangHurm, V.V.HurmHülsmann, A.A.HülsmannKaufel, G.G.KaufelRaynor, B.B.RaynorSchneider, J.J.SchneiderBerroth, M.M.BerrothKöhler, KlausKlausKöhler2022-03-032022-03-031991https://publica.fraunhofer.de/handle/publica/17959410.1016/0167-9317(91)90237-8A high speed 2:1 multiplexer circuit in source coupled FET logic has been developed and fabricated using a recessed gate process for enhancement and depletion transistors with 0.3Mym gate length. First results show a data rate of over 20 Gbit/s at 5 V supply voltage and 250 mW power consumption. The output voltage swing is adjustable between 0.3 V and 0.8 V for a 50 Ohm load. The output level can be varied between plus1 V an minus1 V. Comparison between simulation and measurement shows very good agreement.encommunication systemE/D Transistorhigh-speed switchHochgeschwindigkeitsschalterKommunikationssystemmultiplexersource coupled fet logictest equipment instrumentationTestgerät62166720 Gbit/s 2 to 1 multiplexer using 0.3 mym gate length double pulse doped Quantum Well GaAs/AlGaAs transistors.20 Gbit/s 2 zu 1 Multiplexer unter Verwendung von Doppel Puls dotiertem Quantum Well GaAs/AlGaAs Transistoren mit einer Gate-Länge von 0.3 mymjournal article