Sene, B.B.SeneKnapp, H.H.KnappLi, H.H.LiKammerer, J.J.KammererMajied, S.S.MajiedAufinger, K.K.AufingerFritzin, J.J.FritzinReiter, D.D.ReiterPohl, N.N.Pohl2022-03-142022-03-142019https://publica.fraunhofer.de/handle/publica/40754710.1109/BCICTS45179.2019.8972772This work presents the design of a power amplifier (PA) with an AC-coupled common-emitter and common-base stage in a 130 nm SiGe BiCMOS technology. The amplifier operates in the D-band and consists of two driving stages followed by an output power stage. At 143 GHz a small signal gain of 39.8 dB and a maximum saturated output power (P SAT ) of 16 dBm is achieved. The PAE peak value is 5.4 %, while the chip draws 220 mA from a 3.3 V power supply. Including pads the chip consumes an area of 0.66 mm 2 . To the best of the authors' knowledge this is the highest value for P SAT reported in this frequency range using silicon-based technologies.en621conference paper