ESD circuit simulation for the prevention of ESD failures. Application to products in a 0.18 µm CMOS technology

Wolf, H.H.WolfGieser, H.H.GieserStadler, W.W.StadlerEsmark, K.K.Esmark2022-03-092022-03-092002https://publica.fraunhofer.de/handle/publica/33989510.1109/RELPHY.2002.996630This paper describes the ESD circuit simulation of MOS transistors processed in a 0.18 µm CMOS technology. The extended model simulates the breakdown between the external base and the emitter diffusion as well as the forward bias condition. The applied parameter extraction methodology also comprises device simulation. Including the transient behavior the model is verified by means of test circuits. Moreover, this approach simulates "real world" failures of product circuits.enelectrostatic dischargedevice simulationparameter extraction621ESD circuit simulation for the prevention of ESD failures. Application to products in a 0.18 µm CMOS technologyconference paper