Okuno, J.J.OkunoKunihiro, T.T.KunihiroKonishi, K.K.KonishiMaemura, H.H.MaemuraShuto, Y.Y.ShutoSugaya, F.F.SugayaMaterano, M.M.MateranoAli, T.T.AliLederer, M.M.LedererKuehnel, K.K.KuehnelSeidel, K.K.SeidelSchroeder, U.U.SchroederMikolajick, T.T.MikolajickTsukamoto, M.M.TsukamotoUmebayashi, T.T.Umebayashi2022-03-152022-03-152021https://publica.fraunhofer.de/handle/publica/41291210.1109/IMW51353.2021.94395952-s2.0-85107685978A novel 64 kbit one-transistor one-capacitor (1T1C) ferroelectric random access memory (FeRAM) array based on ferroelectric Hf0.5Zr0.5O2 (HZO) was proposed in a prior report. However, this array requires a low operation voltage for integration into advanced technology nodes, and its practical endurance remains unclear. To address these limitations, this study experimentally demonstrates the improved characteristics of a ferroelectric HfO2-based 1T1C FeRAM array. Thickness scaling of the ferroelectric HZO contributes to low-voltage operation of 1T1C FeRAMs, yielding 100% bit functionality at an operation voltage of 2.0 V and operating speed of 16 ns. Furthermore, the endurance performance of the 1T1C FeRAM memory array was investigated for the first time. Excellent cycling endurance (>108 cycles) at an accelerated stress voltage of 3.5 V at 85°C was experimentally observed. The 1 ppm RBER at 2.0 V, 100 ns, and 85°C operation was predicted to be >1018 cycles, based on t he dependence of time to breakdown on the stress voltage. This technology matches the requirements of last-level cache and low-power systems on chips for Internet of things applications.en621conference paper