Under CopyrightKallinger, BirgitBirgitKallingerBerwian, PatrickPatrickBerwianFriedrich, JochenJochenFriedrichHecht, ChristianChristianHechtPeters, DethardDethardPetersFriedrichs, PeterPeterFriedrichsThomas, BerndBerndThomas2022-03-1110.10.20122012https://publica.fraunhofer.de/handle/publica/37659310.24406/publica-fhg-3765934H-SiC PiN diodes for 6.5 kV were manufactured on both 4° and 8° off-cut substrates and subjected to an electrical stress test on wafer level and subsequent analysis of structural defects present in the active area of the diodes. For 8° off-cut diodes, the electrical characteristics with respect to leakage current and forward voltage drift are worse than the electrical characteristics of 4° off-cut diodes. Furthermore, a large number of stacking faults was found in 8° off-cut diodes, but little evidence for bipolar degradation was found in 4° off-cut diodes. Therefore, bipolar degradation was significantly reduced by avoiding BPDs in the active area of PiN diodes, i.e. by the use of 4° off-cut substrates. Furthermore, a strong correlation was found between the electrical screening test on wafer level and critical defects.enpin diodespower electronicssynchrotron x-ray topographydislocationsstacking fault670620530poster