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  • Publication
    An analysis on retention error behavior and power consumption of recent DDR4 DRAMs
    ( 2018)
    Mathew, Deepak M.
    ;
    Schultheis, Martin
    ;
    Rheinländer, Carl C.
    ;
    Sudarshan, Chirag
    ;
    Weis, Christian
    ;
    Wehn, Norbert
    ;
    Jung, Matthias
    DRAM technology is scaling aggressively that results in high leakage power, worse data retention time behavior, and large process variations. Due to these process variations, vendors provide large guard bands on various DRAM currents and timing specifications that are over pessimistic. Detailed knowledge on the DRAM retention behavior and currents for the average case allow to improve memory system performance and energy efficiency of specific applications by moving away from worst case behavior. In this paper, we present an advanced measurement platform to investigate off-the-shelf DDR4 DRAMs' retention behavior, and to precisely measure various DRAM currents (IDDs and IPPs) at a wide range of operating temperatures. Error Checking and Correction (ECC) schemes are popular in correcting randomly scattered single bit errors. Since retention failures also occur randomly, ECCs can be used to improve DRAM retention behavior. Therefore, for the first time, we show the influence of ECC on the retention behavior of recent DDR4 DRAMs, and how it varies across various DRAM architectures considering detailed structure of the DRAM (true-cell devices/mixed-cell devices).
  • Publication
    Electromagnetic modeling and optimization of packaged photodetector modules for 100 Gbit/s applications
    ( 2008)
    Jiang, C.
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    Krozer, V.
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    Johansen, T.K.
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    Bach, H-G.
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    Mekonnen, G-G.
    ;
    Zhang, R.
    ;
    Pech, D.
    In this paper, we propose an accurate full 3D EM behavioral model of PD chips for the first time. The model, which is meshed at 130 GHz, runs for about 17 minutes on an Intel Core2 Duo CPU@3 GHz PC with 3.5 GB of RAM. The impact of various parameters in wire- bonding transitions for transmission characteristic is summarized in the Table I. When numbers of bonding wires are placed separately all through strips of CBCPWs as well as keeping an optimized gap of transitions, more than 10 GHz bandwidth improvement can be achieved compared the worst case. We also notice that optimization on bonding wires does not significantly improve the fast decay beyond 60 GHz. Further investigation and optimization of the transition is required including a redesign of the CBCPW.
  • Publication
    Random access fiber loop optical memory with active switching and amplifying elements for optical ATM systems
    ( 1991)
    Ludwig, R.
    ;
    Deitrich, E.
    ;
    Grosskopf, G.
    ;
    Kuller, L.
    ;
    Pieper, W.
    ;
    Weber, H.G.
    A fiber loop optical memory with active switching and amplifying elements and capable of random access was investigated. Transmission of 1.7 Gbit/s, 512 bit ATM-cells was measured at BER=10-9 for up to 7 fiber loop round trips.
  • Publication
    BER measurements in random access fibre loop optical memory
    ( 1991)
    Dietrich, E.
    ;
    Grosskopf, G.
    ;
    Kuller, L.
    ;
    Ludwig, R.
    ;
    Pieper, W.
    ;
    Weber, H.G.
    An investigation of a fibre loop optical memory with active switching and amplifying elements and capable of random access is presented. Transmission of 1.7 Gbit/s, 512 bit ATM-cells is achieved at BER=10-9 for up to seven fibre loop round trips.