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Author: Taffoni, G. ×

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  • Publication
    Next generation of Exascale-class systems
    ( 2018)
    Katevenis, M.
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    Ammendola, R.
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    Biagioni, A.
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    Cretaro, P.
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    Frezza, O.
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    Lo Cicero, F.
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    Lonardo, A.
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    Martinelli, M.
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    Paolucci, P.S.
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    Pastorelli, E.
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    Simula, F.
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    Vicini, P.
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    Taffoni, G.
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    Pascual, J.A.
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    Navaridas, J.
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    Luján, M.
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    Goodacre, J.
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    Lietzow, B.
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    Mouzakitis, A.
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    Chrysos, N.
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    Marazakis, M.
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    Gorlani, P.
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    Cozzini, S.
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    Brandino, G.P.
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    Koutsourakis, P.
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    Ruth, J. van
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    Zhang, Y.
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    Kersten, M.
    The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an European Exascale-class supercomputer. The common goal is designing and implementing a physical rack prototype together with its cooling system, the non-volatile memory (NVM) architecture and a unified low-latency interconnect able to test different options for network and storage. Furthermore, the consortium goal is to provide real HPC applications to validate the system. In this paper we describe the unified data and storage network architecture, reporting on the status of development of different testbeds and highlighting preliminary benchmark results obtained through the execution of scientific, engineering and data analytics scalable application kernels.
  • Publication
    The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems
    ( 2016)
    Katevenis, M.
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    Chrysos, N.
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    Marazakis, M.
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    Mavroidis, I.
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    Chaix, F.
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    Kallimanis, N.
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    Navaridas, J.
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    Goodacre, J.
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    Vicini, P.
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    Biagioni, A.
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    Paolucci, P.S.
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    Lonardo, A.
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    Pastorelli, E.
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    Cicero, F.L.
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    Ammendola, R.
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    Hopton, P.
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    Coates, P.
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    Taffoni, G.
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    Cozzini, S.
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    Kersten, M.
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    Zhang, Y.
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    Sahuquillo, J.
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    Lechago, S.
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    Pinto, C.
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    Lietzow, B.
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    Everett, D.
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    Perna, G.
    ExaNest is one of three European projects that support a ground-breaking computing architecture for exascale-class systems built upon power-efficient 64-bit ARM processors. This group of projects share an 'everything-close' and 'share-anything' paradigm, which trims down the power consumption - by shortening the distance of signals for most data transfers - as well as the cost and footprint area of the installation - by reducing the number of devices needed to meet performance targets. In ExaNeSt, we will design and implement: (i) a physical rack prototype and its liquid-cooling subsystem providing ultra-dense compute packaging, (ii) a storage architecture with distributed (in-node) non-volatile memory (NVM) devices, (iii) a unified, low-latency interconnect, designed to efficiently uphold desired Quality-of-Service guarantees for a mix of storage with inter-processor flows, and (iv) efficient rack-level memory sharing, where each page is cacheable at only a single node . Our target is to test alternative storage and interconnect options on actual hardware, using real-world HPC applications. The ExaNeSt consortium brings together technology, skills, and knowledge across the entire value chain, from computing IP, packaging, and system deployment, all the way up to operating systems, storage, HPC, big data frameworks, and cutting-edge applications.