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Author: Glein, Robért ×

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Now showing 1 - 3 of 3
  • Publication
    On Adaptive Single-Event Effect Mitigation in Reconfigurable FPGAs
    (Fraunhofer Verlag, 2019)
    Glein, Robért
    This thesis discusses adaptive mitigation of non-destructive radiation effects (static single-event effect) in environments with varying radiation (e.g. Earth orbits). The adaptive mitigation scheme overcomes the problem of the permanent overhead of static mitigation caused by systems designed according to the worst case condition. It is implemented in a single FPGA including sensor primitives, radiation condition analysis, and reconfiguration in an autonomous manner. The system is evaluated with the parameter of the performability, which is a combination of performance and availability. The optimum of this performability is improved by a factor of 2.32 in a geostationary Earth orbit compared to the state of the art. During the observation interval of 7.67 years (2010 to 2017), the FPGA is configured with triple modular redundancy less than 10 % of the time. During the rest of the time (>90 %) the FPGA may perform a more sophisticated digital signal processing or may save power. Furthermore, this thesis provides systems designers a useful tool to determine which kind of mitigation is appropriate and most beneficial.
  • Publication
    A self-adaptive SEU mitigation system for FPGAs with an internal block RAM radiation particle sensor
    ( 2014)
    Glein, Robért
    ;
    Schmidt, Bernhard
    ;
    Rittner, Florian
    ;
    Teich, Jürgen
    ;
    Ziener, Daniel
    In this paper, we propose a self-adaptive FPGA- based, partially reconfigurable system for space missions in order to mitigate Single Event Upsets in the FPGA configuration and fabric. Dynamic reconfiguration is used here for an on-demand replication of modules in dependence of current and changing radiation levels. More precisely, the idea is to trigger a redundancy scheme such as Dual Modular Redundancy or Triple Modular Redundancy in response to a continuously monitored Single Event Upset rate measured inside the on-chip memories itself, e.g., any subset (even used) internal Block RAMs. Depending on the current radiation level, the minimal number of replicas is determined at run- time under the constraint that a required Safety Integrity Level for a module is ensured and configured accordingly. For signal processing applications it is shown that this autonomous adaption to the different solar conditions realizes a resource efficient mitigation. In our case study, we show that it is possible to triplicate the data throughput at the Solar Maximum condition (no flares) compared to a Triple Modular Redundancy implementation of a single module. We also show the decreasing Probability of Failures Per Hour by 2 × 104 at flare-enhanced conditions compared with a non-redundant system. Our work is a part of the In-Orbit Verification of the Heinrich Hertz communication satellite.
  • Publication
    An on-board processor for in-orbit verification based on a multi-FPGA platform
    ( 2011)
    Hofmann, Alexander orcid-logo
    ;
    Glein, Robért
    ;
    Kollmannthaler, Bernd
    ;
    Wansch, Rainer
    The increasing demand for higher data rates, smaller antenna apertures, or less power at the uplink for mobile devices requires air-interface and application specific processing, especially for telecommunication satellites. Only on satellites for dedicated applications or with a short limited lifetime, on-board processing is partly used, but processing on-board improves the system performance or increases the system capacity in several cases. Today's on-board processing for satellite communication is mostly based on ASIC (Application Specific Integrated Circuit) chips, which have their main drawback in the limited flexibility. In order to demonstrate and validate the flexibility of an FPGA-based on-board processor (OBP) for space applications the Fraunhofer IIS is involved in a so-called in-orbit verification (IOV) payload on the Heinrich-Hertz-Satellite. During the development of an on-board processor for space applications, the main challenge is to ensure a typical life time of 15 years for the hard-, firm- and software under the given environmental conditions. Alternatively, an FPGA platform can be reconfigured for novel communication protocols. In order to investigate new standards for telecommunication satellite systems, the Fraunhofer IIS is developing an OBP platform, based on four FPGAs. The OBP will be embedded into the H2Sat satellite, which will be launched in 2016 and will be located on a geostationary earth orbit (GEO). To the best of our knowledge, this is the first completely reconfigurable platform based on four leading-edge radiation-hardened FPGAs in the geosynchronous orbit for telecommunication satellites.