Virtual prototyping, verification and validation framework for automotive using SystemC, SystemC-AMS and UVM-SystemC
Paper presented at ERTS2 2014, Embedded Real Time Software and Systems, 5th - 7th February 2014, Toulouse, France
Electronics for automotive systems are characterized by an increasing complexity and a more and more tighter interaction between analog, digital hard- and software. They consist of a huge portion of embedded software, which executes on large (regarding the number of devices) digital subsystems and controlling and assisting analog devices. Furthermore, automotive electronics deeply interacts with the non-electronic environment. Due to this increasing complexity of automotive electronic devices the verification becomes more and more challenging. Today, existing verification methodologies are mostly focused on pure digital devices and are completely decoupled from analog verification. Additionally, the existing methodologies tend to focus on implementation level verification. They do not meet the requirements of state of the art automotive applications. Based on the powerful 3-uple (Universal Verification Methodology (UVM) principles, SystemC, SystemC AMS extensions), this paper shows how the principles of the new UVM methodology can be soundly enhanced to offer to the test designer a flexible framework for the virtual prototyping of multi-discipline testbenches that supports both digital and Analog Mixed-Signal (AMS) at the architectural level. The paper clearly details the architecture of the reusable verification IPs and the synchronization mechanisms used to simultaneously manage test at a high level of abstraction (test sequences) and communicate with the AMS DUT at the pin level. The presented techniques are applied to two operational case study, a full-fledged programmable filter testbench, and then applied to a smart power supply module on an automotive Electronic Control Unit.