Charge-injection photogate pixel fabricated in CMOS silicon-on-insulator technology

Concept, theoretical analysis, and experimental results obtained from a charge-injection photogate (CI-PG) pixel detector fabricated in CMOS silicon-on-insulator (SOI) technology are presented. The charge collected in the photodetector during a certain charge collection (integration) time is injected into the substrate for readout. This readout principle presents a huge internal photocurrent amplification (~104), taking place in the photodetector, obtained through the "time-compression" approach. Here, the readout circuitry is fabricated on highly doped, 200 nm thick, SOI film, while the photogate detector is fabricated on higher-resistivity handle-wafer. The latter, together with the 30 V biasing possibilities, enhances the quantum efficiency of the pixel, especially for irradiations with wavelengths in the near-infra-red part of the spectra.