The highest potential for future single chip packages has the wafer level approach: The package is completed directly on the wafer then singulated by dicing for the assembly in a nip chip fashion. The technological structure of this double-ball CSP is a pad redistributed die with a solder ball array. A stress compensation layer (SCL) embeds the solder balls before second solder balls are stencil printed or placed on top of embedded balls. The reliability of the wafer-level CSP presented here was evaluated. The test chip was a 1 cm x 1 cm square chip which was redistributed to an 14 x 14 ball array with a pitch of 0.5". JEDEC Level 3, 1000 cycles AATC (-55'C/+I25'C) and 48h Autoclave on component level were passed. On board level 1000 hours humidrty storage at 85°C (8985 test) were passed and only 20% of the WL-CSPs had opens after 1000 cycles -59+125'C.
