LVDS I/O cells with rail-to-rail receiver input for SONET/SDH at 1.25 Gb/s
Abstract
Low voltage differential signaling (LVDS) has developed as a data transmission standard for on-chip, onboard/backplane or cable connections. This report covers design criteria and measurement results of 1.25 Gb/s LVDS I/O cells serving various application requirements (e. g. SONET/SDH) and developed for 0.25 µm and 0.18 µm standard digital CMOS processes. Especially the design of a rail-to-rail input stage will be described.
