Matrix method for latch-up free demonstration in a triple-well bulk-silicon technology

A CMOS inverter made in bulk silicon by triple-well technology, which was proposed in earlier papers, is examined with respect to its latch-up behavior. With this exemplary circuit and a matrix like scheme it can be proved that the conditions for the occurence of the latch-u effect are not met in any case. It is demonstrated for the first time that this type of technology leads to completely latch-up free CMOS ciruits in bulk silicon and, therefore, extremely good hardness against transient radiation induced effects can be achieved without using SOI (Silicon On Insulator) and SOS (Silicon On Sapphire). Improved insensitivity to SEU (Single Event Upset can be expected.