Role of parasitic capacitances in power MOSFET turn-on switching speed limits: A SiC case study

This paper describes the effect of MOSFET internal capacitances on the channel current during the turn-on switching transition: an intrinsic theoretical switching speed limit is found and detailed mathematically. The set of analytical equations is solved and the effect of the displacement currents is highlighted with ideal simulated waveforms. A laboratory experiment is thus performed, in order to prove the theoretical predictions: a 25 mO SiC CREE power MOSFET is turned on in a no-load condition (zero drain current), starting from different drain-source voltage values. Finally, a LTSpice equivalent circuit model is also built, to better simulate the experimental behavior of the device, adding circuit strain components and other non-idealities to the overall model. A good match between measurements and simulations is observed, mostly validating either the theoretical assumptions and the presented model.