Multi-Scheduling Crossbar Mapping and Design-Space Exploration of MAGIC-Based ReRAM Arithmetic Circuits for In-Memory Computing

Memristor-Aided Logic (MAGIC)-based In-Memory Computing (IMC) executes Boolean operations directly within crossbar arrays, addressing the von Neumann bottleneck. However, the efficiency of MAGIC-based arithmetic circuits strongly depends on mapping strategies. This work presents a unified, parallel row-wise, multi-scheduling-aware framework for efficient crossbar mapping of MAGIC-based adders, multipliers, and dividers. The proposed design flow integrates automated Register-Transfer Level (RTL) generation, NOT/NOR-constrained logic synthesis, and multiple scheduling strategies, namely As Soon As Possible (ASAP), As Late As Possible (ALAP), and Resource-Constrained (RC), to systematically extract micro-operations and evaluate latency, memristor counts, crossbar size, and energy. Comprehensive benchmarking across multiple arithmetic architectures (8–64-bit adders/multipliers and up to 128/64-bit division) demonstrates that RC scheduling consistently reduces crossbar size without increasing logic depth. Among the evaluated designs, Brent–Kung (BK) adders and Dadda Tree (DT) multipliers provide the best scalability, while Restoring Array Dividers offer high efficiency. The proposed mapping framework achieves reduced latency and improved area–latency trade-offs compared to prior MAGIC designs, and comparative evaluation shows competitive performance for adders and substantially lower latency with improved scalability for multiplier architectures compared with representative MAC-, MAJ-, and AIG-based IMC implementations.