• English
  • Deutsch
  • Log In
    Password Login
    Research Outputs
    Fundings & Projects
    Researchers
    Institutes
    Statistics
Repository logo
Fraunhofer-Gesellschaft
  1. Home
  2. Fraunhofer-Gesellschaft
  3. Scopus
  4. Optimizing the Post Quantum Signature Scheme CROSS for Resource Constrained Devices
 
  • Details
  • Full
Options
2026
Journal Article
Title

Optimizing the Post Quantum Signature Scheme CROSS for Resource Constrained Devices

Abstract
Post-quantum cryptosystems are currently attracting significant research efforts due to the continuous improvements in quantum computing technologies, which led the National Institute of Standards and Technology (NIST) to open standardization competitions to foster proposals and public scrutiny of cryptosystems and digital signatures. Whilst NIST has chosen, after four selection rounds, three digital signature algorithms, it also has opened a new selection process as the chosen candidates were either relying only on lattice-based computationally hard problems, or had unsatisfactory performance figures. In this work, we propose two optimized implementations of the Codes and Restricted Objects Signature Scheme (CROSS) targeting the Cortex-M4 platform. One implementation targets the minimal possible stack size while the other trades some memory space for performance optimization using DSP instructions for some performance critical arithmetic operations. We show that all parameter sets fit within at maximum 24 kB of stack which corresponds to a reduction by a factor of 15 to 45 with respect to the reference implementation. The memory footprint of our implementation, taking the size of the signature also into account, is less than 128 kB. We additionally outline different stack reduction options which allow for a fine grained trade-off between memory footprint and performance of the algorithm. Notably, we also show that our memory optimizations alone have no significant performance impact on the signature verification of CROSS while we even achieve a speed-up factor of up to 1.7 when taking the stack and speed optimizations into account.
Author(s)
Schupp, Jonas
Technische Universität München
Gianvecchio, Marco
Politecnico di Milano
Barenghi, Alessandro
Politecnico di Milano
Karl, Patrick
Technische Universität München
Pelosi, Gerardo
Politecnico di Milano
Sigl, Georg  
Fraunhofer-Institut für Angewandte und Integrierte Sicherheit AISEC  
Journal
IACR transactions on cryptographic hardware and embedded systems  
Open Access
File(s)
Download (762.86 KB)
Rights
CC BY 4.0: Creative Commons Attribution
DOI
10.46586/tches.v2026.i3.224-246
10.24406/publica-9678
Additional link
Full text
Language
English
Fraunhofer-Institut für Angewandte und Integrierte Sicherheit AISEC  
Keyword(s)
  • Code-based signature

  • Post-quantum Signature

  • Software optimized implementation

  • Cookie settings
  • Imprint
  • Privacy policy
  • Api
  • Contact
© 2024