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VHDL-AMS model of a 40 M/s 12 bits pipeline ADC
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2006
Conference Paper
Title
VHDL-AMS model of a 40 M/s 12 bits pipeline ADC
Author(s)
Diaz-Madrid, J.-A.
Domenech-Asensi, G.
University of Cartagena
Lopez-Alcantud, J.A.
University of Cartagena
Neubauer, H.
Mainwork
International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2006. Proceedings
Conference
International Conference Mixed Design of Integrated Circuits and Systems (MIXDES) 2006
DOI
10.1109/MIXDES.2006.1706641
Language
English
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