Impact of quantization noise errors in FPGA based WLAN timing synchronization with the Schmidl and COX algorithm

The implementation of accurate solutions to synchronize the transceiver's clocks in real-time operations plays a major role in the current development of communication systems. Considering the orthogonal frequency division multiplexing (OFDM)-based systems, adopted for the deployment of fifth-generation mobile networks (5G), industrial networks, and the wireless local area network (WLAN) standard, several reported solutions focus on field-programmable gate array (FPGA) designs for the clock synchronization in real-time operations. However, reported solutions describe with minor details the impact of the introduced quantization noise error (QNE) based on the implemented bit-width. Their studies provide insights to implement digital solutions of reduced complexity. The current article provides theoretical expressions to characterize accuracy and precision while synchronizing the transmitter's clock. The presented analysis is intended to support designers to evaluate the c lock synchronization design considering the bit-width for implementing the given system.