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A 32 bit 15M flop floating point programmable signal processor architecture for VLSI implementation
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1985
Conference Paper
Titel
A 32 bit 15M flop floating point programmable signal processor architecture for VLSI implementation
Author(s)
Hesson, J.H.
Hauptwerk
IEEE International Conference on Acoustics, Speech, and Signal Processing 1985. Proceedings
Konferenz
International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 1985
Language
English
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Fraunhofer-Institut für Mikroelektronische Schaltungen und Systeme IMS
