Prof. Dr.-Ing.

Hoene, Eckart

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  • Patent
    Folienkondensator mit integriertem Wärmeableitelement und Verfahren für dessen Herstellung
    ( 2023-07-27)
    Hoene, Eckart
    ;
    Seidenstücker, Dominik
    ;
    Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
    Es wird ein Folienkondensator (10) vorgeschlagen, der wenigstens ein erstes Kondensatormodul (2) und ein zweites Kondensatormodul (2), die jeweils eine alternierende Abfolge von dielektrischen Kunststoffschichten (3) und elektrisch leitfähigen Metallschichten (4) umfassen und wenigstens einen ersten nach außen geführten elektrischen Anschluss (6) und wenigstens einen zweiten nach außen geführten elektrischen Anschluss (6), wobei jeder der Anschlüsse (6) mit dem ersten und mit dem zweiten Kondensatormodul (2) elektrisch leitend verbunden ist, aufweist. Weiterhin umfasst der Folienkondensator wenigstens ein erstes Wärmeableitelement (12), das zwischen dem ersten und zweiten Kondensatormodul (2) angeordnet ist und das entweder mit dem ersten oder mit dem zweiten elektrischen Anschluss (6) elektrisch leitfähig und thermisch leitfähig verbunden ist, so dass Wärme der Kondensatormodule (2), die von dem Wärmeableitelement (12) aufgenommen wird, über den entsprechend verbundenen Anschluss (6) nach außen führbar ist.
  • Publication
    Presentation of a Reliable Molded Power-PrePackage
    ( 2022)
    Thomas, Tina
    ;
    Rämer, Olaf
    ;
    Nguyen, Thanh Duy
    ;
    Hoene, Eckart
    ;
    Braun, Tanja
    ;
    Liu, Chunlei
    ;
    Pavliček, Niko
    Present paper introduces a package alternative to commercially available single power chips, embedded into printed circuit boards on chip scale size. It addresses assembly and interconnect technology for power electronic devices, namely the packaging of bare power dies into a robust package with superior thermal performance and reliability. Use of Cu columns as top side contact and isotropic encapsulation material enable highly reliable packages with thermal path on bottom and top side. The study investigates the feasibility of applied assembly and encapsulation processes regarding mass production. Package reliability has been evaluated by Active Power Cycling and Moisture Sensitivity Level tests.
  • Publication
    Pareto front system optimization on the example of a motor drive
    ( 2022)
    Hoffmann, Stefan
    ;
    Hoene, Eckart
    During the design process of a power electronic system a variety of operating and component parameters can be varied and combined. Therefore, a huge number of design possibilities arise. In this paper, Pareto front optimizations are utilized to investigate the maximum power density of 3-phase motor inverters. First, the analytical power loss, volume, EMC and thermal models are briefly presented and validated on a 63 kW motor drive system. These models are used for fundamental investigations on the dependency of the optimum switching frequency and power density on the rated power of the motor drive. Combinations of model parameters form a Pareto front analysis.
  • Publication
    Design Tool for Temperature Estimation on PCB
    ( 2022)
    Schroeder, Bernd
    ;
    Hoffmann, Stefan
    ;
    Mueller, Olaf
    ;
    Stube, Bernd
    ;
    Hoene, Eckart
    The paper presents a novel thermal analysis approach based on an estimation of current density, power dissipation and temperature distribution of a printed circuit board. The implemented algorithms are integrated in a design tool that can be used as an add-on tool via interfaces to commercial EDA tools. The calculations are based on imported layout data from the EDA tools and not on Gerber data. The current density is calculated with a separate PEEC solver. The developed design tool automatically generates the necessary 3D model, activates the PEEC solver and extracts its calculation results. Subsequently, the implemented thermal solver of the design tool calculates the power dissipation and temperature distribution for a previously assigned current. This efficiently supports the PCB designer already during the layout process. The method is validated by simulations and measurements on typical boards.
  • Publication
    Compact Power Electronics System Fabrication by Sintering and Lamination of Components into Build-up Layers of the Printed Circuit Boards
    ( 2022)
    Löher, Thomas
    ;
    Zeiter, Oleg
    ;
    Hoene, Eckart
    ;
    Ostmann, Andreas
    ;
    Schneider-Ramelow, Martin
    Power electronic systems equipped with wide band gap semiconductors like SiC and GaN are attracting increasing attention due to the superior functionality of these materials. Especially for automotive, aerospace and energy grid applications a large market potential is expected, which is reflected in massive investments in respective semiconductor development and fabrication. In order to make full use of the semiconductor properties, however, not only the single components but the whole system has to be taken into account. Major aims in system optimization is the reduction of dc voltage link inductance, optimization of heat dissipation and an overall miniaturization and robustness of modules. Thus, the shortening of interconnect length, the integration of thermal dissipation structures and a compact three-dimensional build-up of systems are at the core of ongoing developments in power electronics. During the past decade, embedding of electronic components into printed circuit board has proven to be a highly promising technology for large-scale fabrication that can meet these requirements. In this paper we present a fabrication approach that is applicable in any printed circuit board fabrication, since only standard equipment is used. As basic building blocks, pre-packaged power semiconductors were used. The fabrication of these will be described briefly. Power components of this type are now commercially available from some suppliers. For the module fabrication, first a typical insulated metal substrate is fabricated. Onto the copper structures, sinter paste is printed to mount pre-packages and vertical resistors. A prepreg-layup is then assembled which surrounds the components. The final layer of the stack is a two-layer power core for electrical routing, which is equipped with sinter depots for top side connection of the components. The stack is laminated with an initial pressure and temperature overshoot in order to facilitate the sintering process. Subsequently the profile resumes conventional parameters in order to cure the prepreg and finalize the lamination process. Surface mounted ceramic capacitors soldered to the top complete the low-impedance dc-link buffer circuit. Damping resistors were embedded into the PCB module, which besides compactness enables an excellent cooling of the module. This technology pushes the fast-switching SiC and GaN power semiconductors to the next step. The drastic reduced switching overvoltage of only 4%, demonstrated for 950 V operation, enables a significantly improved utilization of the semiconductors.