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Alternative UBM for Lead Free Solder Bumping using C4NP

: Ruhmer, K.; Laine, E.; O'Donnell, K.; Kostetsky, J.; Hauck, K.; Manessis, D.; Ostmann, A.; Töpper, M.; Jürgensen, N.


Institute of Electrical and Electronics Engineers -IEEE-; IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE 57th Electronic Components and Technology Conference 2007. Vol.1 : Sparks, NV, 29 May - June 1, 2007
Piscataway, NJ: IEEE, 2007
ISBN: 1-4244-0984-5
ISBN: 1-4244-0985-3
Electronic Components and Technology Conference (ECTC) <57, 2007, Reno/Nev.>
Fraunhofer IZM ()

Microelectronic packaging continues the migration from wire bond to flip chip first level interconnect (FLI) to meet aggressive requirements for improved electrical performance, reduced size and weight. The interconnect pitch is being predicted by forecasts like ITRS to be reduced to 100 um and below for full array I/O layout. For wafer bumping, solder electroplating is commonly employed, especially for fine pitch applications. Wafer level chip scale packaging (WLCSP) typically utilizes solder sphere placement technology to manufacture the bumps. In WLCSP, pitch and solder ball size are usually much higher and the number of I/O much lower than for Flip Chip in Package (FCiP) applications. C4NP (Controlled Collapse Chip Connection New Process) has proven to be suitable for a broad range of solder bump pitches, encompassing FCiP to CSP bump dimensions. As the industry migrates to 300mm wafer processing and lead-free flip chip interconnect, C4NP is establishing itself as a viable solder bumping alternative. Due to its nature as a bump transfer technology, it is expected that the bumping yield will be very high, since filled molds can be inspected prior to solder transfer to the wafer. Yield is a major issue for the highest I/O applications like microprocessors. The under bump metallurgy (UBM) structure is a critical component of any solder interconnect system. The UBM typically provides three functions: adhesion to underlying dielectric and metal, barrier to protect the silicon circuitry, and a solder wettable surface.