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Interconnect Aware Power Optimization of Low Swing Driver for Multi-Chip Interfaces

: Chaudhary, Muhammad Waqas; Heinig, Andy; Choubey, Bhaskar


Institute of Electrical and Electronics Engineers -IEEE-:
27th IEEE International Conference on Electronics Circuits and Systems, ICECS 2020. Conference Proceedings : Virtual conference, November 23-25, 2020
Piscataway, NJ: IEEE, 2020
ISBN: 978-1-7281-6045-0
ISBN: 978-1-7281-6044-3
4 S.
International Conference on Electronics, Circuits and Systems (ICECS) <27, 2020, Online>
European Commission EC
EFRE; 10037523; ARAMID
radAR für AutonoMes fahren - eInsetzbar von jeDermann
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
Fraunhofer IMS ()
driver; multi-chip communication; optimization; source follower

Communication between dies in a multi-chip system requires low power consumption. Silicon area consumed by drivers should also be minimized. Traditionally, drivers for multichip communication are designed for maximum channel loss estimated in a given system. This design strategy leads to higher power consumption even when the channel is extremely short and low loss. This paper proposes an optimization approach for interconnect aware low swing driver with a case study of source follower based architecture. It is shown that by using this strategy, the driver can reach an energy efficiency of 0:15 pJ=bitat 1Gb=s data rate on 3:8mm organic substrate interconnect.