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Implementation of an integrated differential readout circuit for transistor-based physically unclonable functions

: Willsch, Benjamin; Müller, Kai-Uwe; Zhang, Qi; Hauser, Julia; Dreiner, Stefan; Stanitzki, Alexander; Kappert, Holger; Kokozinski, Rainer; Vogt, Holger


Institute of Electrical and Electronics Engineers -IEEE-; Institute of Electrical and Electronics Engineers -IEEE-, Austria Section:
25th Austrochip Workshop on Microelectronics, Austrochip 2017. Proceedings : 12th October 2017, Linz, Austria
Piscataway, NJ: IEEE, 2017
ISBN: 978-1-5386-3583-4
ISBN: 978-1-5386-3584-1
Austrochip Workshop on Microelectronics (Austrochip) <25, 2017, Linz>
Fraunhofer IMS ()
process variation; spatial variation decomposition; hierarchical median polish

Physically Unclonable Functions (PUFs) offer enticing possibilities to incorporate hardware-based security on semiconductor device level. In order to make efficient use of PUF functionality in lightweight cryptographic applications, a low-overhead implementation in terms of chip area and power consumption is required. In this paper a fully differential readout circuit is proposed that allows the generation of multiple bits from selected pairs of PUF-elements. The IC-design and working principle are explained on basis of a critically-sized nMOS transistor array serving as a PUF-primitive. First results obtained from circuit simulations and wafer-level measurements of 30 PUF-instances fabricated in a 0.35μm CMOS technology are presented. Evaluation of the intra- and inter-Hamming distance with average values of 9.42% and 49.46%, respectively, shows that device identification based on the extracted keys is feasible. In order to increase the number of unique keys obtainable for each PUF-instance layout improvements in form of additional row select connections are proposed.