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3D wafer level packaging by using Cu-through silicon vias for thin MEMS accelerometer packages

: Hofmann, L.; Schubert, I.; Wuensch, D.; Ecke, R.; Vogel, K.; Gottfried, K.; Reuter, D.; Rennau, M.; Schulz, S.E.; Gessner, T.

Abstract (HTML; )

Journal of surface mount technology 30 (2017), Nr.1, 8 S.
ISSN: 1093-7358
Zeitschriftenaufsatz, Elektronische Publikation
Fraunhofer ENAS ()

Technologies for 3D-Wafer Level Packing (WLP) of Micro electro Mechanical Systems (MEMS) are described with respect to devices that find applications in thin packages (e.g. smart cards). An aspired final device thickness in the range of 350…400 µm is achieved by using Cu based Through Silicon Vias (TSV’s) Wafer Level Bonding (WLB) wafer thinning. In particular, two Via Last approaches using TSV’s in the cap wafer and device wafer, respectively, are described.
According to this, two WLB technologies are investigated: glass frit bonding as well as Silicon Direct Bonding (SDB) of Si-SiO2. The first technique has been demonstrated using a MEMS accelerometer including electrical tests and cross sectional analysis.