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Exploring the concurrent execution of HEVC intra encoding algorithms for heterogeneous multi core architectures

: Brandenburg, J.; Stabernack, B.


Cerisier, S. ; Institute of Electrical and Electronics Engineers -IEEE-; European Electronic Chips & Systems design Initiative -ECSI-, Gieres:
Conference on Design and Architectures for Signal and Image Processing, DASIP 2015. Proceedings : Cracow, Poland, 23 - 25 September 2015
Piscataway, NJ: IEEE, 2015
ISBN: 979-10-92279-10-8
ISBN: 978-1-4673-7737-9
ISBN: 978-1-4673-7739-3
ISBN: 979-10-92279-11-5
Conference on Design and Architectures for Signal and Image Processing (DASIP) <2015, Cracow>
Fraunhofer HHI ()

By introducing novel algorithms in the emerging high efficiency video coding (HEVC) standard average bitrate savings of 23% have been achieved in comparison to the H.264/AVC high profile reference encoder for the all intra configuration at the cost of an additional complexity increase. This high algorithmic complexity requires the development and integration of innovative approaches, like different parallelization strategies, heterogeneous designs and/or algorithmic optimizations, resulting in a complex design space. Early design verifications as well as performance evaluations are crucial to realize successful solutions, which meet the functional and non-functional constrains respectively. In this paper we propose a SystemC based heterogeneous multi-core model of an HEVC intra encoder, which is used to explore different design aspects and alternatives. Due to its cycle accurate nature the model is well suited to facilitate various performance evaluations and to drive H W/SW co-optimizations of the explored system, as we will discuss in this paper.