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Cost modelling for embedded component technology

: Baets, J. de; Willems, G.; Ostmann, A.; Kriechbaum, A.; Kostner, H.

International Microelectronics and Packaging Society -IMAPS-:
EMPC 2007, the 16th European Microelectronics and Packaging Conference & Exhibition. Proceedings. Pt. 1 : June 17 - 20, 2007, Oulu, Finland
Oulu, 2007
ISBN: 978-952-997511-2
European Microelectronics and Packaging Conference and Exhibition (EMPC) <16, 2007, Oulu>
Fraunhofer IZM ()

A generic yield and cost model has been developed for a technology to embed silicon dies into printed circuit boards. The process is split into different process blocks, each with its associated cost, yield and test coverage figures. The developed model is a useful tool to analyse the cost factors, and the influence of process yield and testing on the final module yield and cost. Especially for complex boards with expensive dies, process yield is extremely important.