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Realization of power modules by chip embedding technology

: Boettcher, L.; Karaszkiewicz, S.; Manessis, D.; Ostmann, A.

International Microelectronics and Packaging Society -IMAPS-; Global Business Council -GBC-:
IMAPS International Conference and Exhibition on Device Packaging : In Conjunction with the Global Business Council, GBC 2011 Spring Conference
International Conference and Exhibition on Device Packaging <7, 2011, Scottsdale>
Fraunhofer IZM ()

The continuous miniaturization of silicon dies and the need for a further package size reduction, with an equal or better performance and reduced manufacturing cost, are the main drivers for new packaging concepts. The embedding of active and passive components offers a wide range of benefits and potentials. With the use of laminate based technology concepts, components can be moved from surface mount into the build-up layers of substrates by embedding and by that, the third dimension will be available for further layers or assemblies [1]. By exploiting conventional PCB manufacturing practises, this paper will show how component embedding can be implemented in industrial 18"x24" organic substrate formats for large scale system-in-package manufacturing. Embedding allows having conductors not only under but also over a component leading to a 3-dimensional packaging also on top of the embedded components. The component can be electrically connected to the top or to the bot tom conductive layer or to both of them, e.g. in case of power ICs with contacts on both sides. Such embedding approach is very beneficial in the case of power dies for enhanced heat dissipation from the backside of the power die. The Embedding process flow will be thoroughly discussed and results on embedded power MOS dies having a thickness in the range of 150-300m will be shown. The resultant system-in-packages with embedded power die can be ultimately assembled as conventional SMD packages. The paper will also briefly categorize today's embedding technologies.