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Large-area CMOS SPADs with very low dark counting rate

: Bronzi, Danilo; Villa, Federica; Bellisai, Simone; Tisa, Simone; Tosi, Alberto; Ripamonti, Giancarlo; Zappa, Franco; Weyers, Sascha; Durini, Daniel; Brockherde, Werner; Paschen, Uwe


Razeghi, M. (ed) ; Society of Photo-Optical Instrumentation Engineers -SPIE-, Bellingham/Wash.:
Quantum Sensing and Nanophotonic Devices X : January 2013, San Francisco/Calif
Bellingham, WA: SPIE, 2013 (Proceedings of SPIE 8631)
ISBN: 978-0-8194-9400-9
Paper 86311B
Conference "Quantum Sensing and Nanophotonic Devices" <10, 2013, San Francisco/Calif.>
Fraunhofer IMS ()
complementary metal-oxide semiconductor; photodetector; photon counting; single-photon avalanche photodiode

We designed and characterized Silicon Single-Photon Avalanche Diodes (SPADs) fabricated in a high-voltage 0.35 µm CMOS technology, achieving state-of-the-art low Dark Counting Rate (DCR), very large diameter, and extended Photon Detection Efficiency (PDE) in the Near Ultraviolet. So far, different groups fabricated CMOS SPADs in scaled technologies, but with many drawbacks in active area dimensions (just a few micrometers), excess bias (just few Volts), DCR (many hundreds of counts per second, cps, for small 10 µm devices) and PDE (just few tens % in the visible range). The novel CMOS SPAD structures with 50 mm, 100 µm, 200 µm and 500 µm diameters can be operated at room temperature and show DCR of 100 cps, 2 kcps, 20 kcps and 100 kcps, respectively, even when operated at 6 V excess bias. Thanks to the excellent performances, these large CMOS SPADs are exploitable in monolithic SPAD-based arrays with on-chip CMOS electronics, e.g. for time-resolved spectrometers with no need of microlenses (thanks to high fillfactor). Instead the smaller CMOS SPADs, e.g. the 10 µm devices with just 3 cps at room temperature and 6 V excess bias, are the viable candidates for dense 2D CMOS SPAD imagers and 3D Time-of-Flight ranging chips.