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Embedding technology for manufacturing of high density SiP

: Böttcher, L.; Manessis, D.; Karaszkiewicz, S.; Ostmann, A.

International Microelectronics and Packaging Society -IMAPS-, Nordic Chapter:
IMAPS Nordic Annual Conference 2011. CD-ROM : 5-8 June 2011, Dipoli Congress Center, Espoo, Finland
Oslo: IMAPS Nordic, 2011
International Microelectronics and Packaging Society (IMAPS Nordic Annual Conference) <2011, Espoo>
Fraunhofer IZM ()

Technology approaches for the embedding of active and passive components into build up layers of printed circuit boards have been explored during the last ten years. The adaptation of such technologies for industrial fabrication has attracted increasingly interest by manufacturers and first commercial products have been released. Still these technologies are subject of further developments, which will be addressed in this presentation.
The major areas of interest are:
a) Modularization of systems into embedded subsystems and their interconnection,
b) Processes for high density applications
c) Embedding using advanced materials.
d) Embedded power electronics,
The focus of this presentation will mainly cover the first three aspects.
The realization of embedded modules is quite a robust process for different technologies. The process flow, yield and challenges of such technologies for miniaturized modules and power packages will be presented. By nature of the process extremely flat packages can be realized. The routing of electrical contacts from the embedded components to the top and bottom side of the package allows the fabrication of highly versatile package layouts. The flatness and freedom in design makes these packages ideal candidates for package on package stacking. An example will be discussed where a stacked module containing Si chips in different layers realized.
The movement of silicon dies toward finer pad pitch configurations requires the capability and further improvement of ultra fine pitch (UFP) and ultra fine line (UFL) processing.
To handle UFP dies new methodologies were investigated, utilizing face down and face up chip placement. The current study will include the improvement of chip placement and laser via interconnect formation between chip pad and routing layers, but will also introduce new vialess processing to realize the chip/wiring connection.
With the complexity of the needed patterns for embedded UFP chips, with pad pitches down to 60 µm, and the need of working in large panel formats, UFL processing becomes essential for the formation of the routing layers. First feasibility studies of advanced semi additive copper patterning have shown the capability down to lines and spaces of 15 µm. Advanced studies were done to further develop this process technology towards a high process yield. The current study will describe the semi additive patterning process development based on the use of very thin 2 µm copper foils as a base material and the following resist and copper deposition processing. The study will include process details for a needed excellent photo resist adhesion to the base copper, as well as detailed results for the photo resist exposure, development and the final resist removal after Cu deposition.
The investigation of new embedding material combinations is another important task to provide a reliable package. The main focus here is on new materials that offer improved stability and highly reliable packages. Together with material suppliers improved resin formulations as well as the introduction of filler and glass fibers into the resin layers is currently realized and tested.
Finally applications, scenarios for the implementation of embedding technology and concepts for future applications will be discussed.