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Embedding of chips for system in package realization - technology and applications

: Boettcher, L.; Manessis, D.; Ostmann, A.; Karaszkiewicz, S.; Reichl, H.


3rd International Microsystems, Packaging, Assembly & Circuits Technology Conference, IMPACT 2008 : 22 - 24 Oct. 2008, Taipei. Held in conjunction with International Conference on Electronic Materials and Packaging (EMAP)
Piscataway: IEEE, 2008
ISBN: 978-1-4244-3624-8 (print)
ISBN: 978-1-424-43623-1
International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT) <3, 2008, Taipei>
Fraunhofer IZM ()

In this paper the realization of packages and System-in-Packages (SIP) with embedded components will be described. Embedding of semiconductor chips into substrates has several advantages. It allows a very high degree of miniaturization, due to the possibility of sequentially stacking of multiple layers containing embedded components. A further advantage is the beneficial electrical performance by short and geometrically well controlled interconnects. In addition the embedding gives a homogeneous mechanical environment of the chips, resulting in good reliability. As a result of the increasing interest in implementing embedding technologies in an industrial environment, a newly established European project 'HERMES' will focus mainly on industrial adaptation of embedding technologies with an additional scope of furthering also the existing technological capabilities at prototype level. The goal is to realize a new integrated manufacturing concept to offer low cost solution s for high density electronic systems. New manufacturing and technological challenges arise from the industrialization of component embedding technologies. The new process should combine PCB (Printed Circuit Board) technology and die assembly in one production process in order to benefit the most from large-area processing and high-density packaging. Keywords: 3D packaging, embedded chips, Chip in Polymer, System in Package.