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Development of a multi-project fan-out wafer level packaging platform

: Braun, T.; Raatz, S.; Maass, U.; Dijk, M. van; Walter, H.; Hölck, O.; Becker, K.-F.; Töpper, M.; Aschenbrenner, R.; Wöhrmann, M.; Voges, S.; Huhn, M.; Lang, K.-D.; Wietstruck, M.; Scholz, R.F.; Mai, A.; Kaynak, M.


IEEE Components, Packaging, and Manufacturing Technology Society:
ECTC 2017, the 67th Electronic Components and Technology Conference : 30 May-2 June 2017, Lake Buena Vista, Florida. Proceedings
Piscataway, NJ: IEEE, 2017
ISBN: 978-1-5090-6315-4 (online)
ISBN: 978-1-5090-6316-1 (print)
ISBN: 978-1-5090-4332-3 (USB)
Electronic Components and Technology Conference (ECTC) <67, 2017, Buena Vista/Fla.>
Conference Paper
Fraunhofer IZM ()

Fan-Out Wafer Level Packaging (FOWLP) is one of the latest trends in microelectronics packaging. FOWLP has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, low thermal resistance, high RF performance due to shorter interconnects together, as the direct IC connection by thin film metallization instead of wire bonds or flip chip bumps yields low parasitic effects. Especially inductance of FOWLP is much lower compared to FC-BGA packages. In addition the redistribution layer can also integrate embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for System in Package (SiP) and heterogeneous integration. Hence, technology is well suited for RF applications. FOWLP is in volume manufacturing since a couple of years and services are offered in Asia as well as in Europe. But especially for low volume quantities and prototyping no dedicated packaging services are available. Adapting the success story of Si-based Multi-Project Wafer technology that offers fast and cost-effective access to low numbers of chips, Multi-Project Fan-out Wafer Level Packaging might be an option to address heterogeneous integration for the prototyping market. Within this study such a Multi-Project Fan-out Wafer Level Package (MPFOWLP) technology has been developed and evaluated with focus on RF applications. To demonstrate an entire prototyping run Si dies from a Multi-Project Wafer were used. For technology evaluation six different chips have been selected where five of them were functional dies for application frequencies up to 120 GHz. Additionally one dedicated test die was used, allowing on the one hand RF characterization of the technology approach and on the other hand interconnect testing and reliability characterization.