Fraunhofer-Gesellschaft

Publica

Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Thermal analysis and optimization of 2.5D and 3D integrated systems with wide I/O memory

 
: Heinig, Andy; Fischbach, Robert; Dittrich, Michael

:
Postprint urn:nbn:de:0011-n-3240262 (702 KByte PDF)
MD5 Fingerprint: 7a958640b8cd0d7e629300d5894b2d8a
© IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Created on: 3.2.2015


Institute of Electrical and Electronics Engineers -IEEE-; IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2014. Vol.1 : 27 - 30 May 2014, Lake Buena Vista (Orlando), FL, USA
Piscataway, NJ: IEEE, 2014
ISBN: 978-1-4799-5268-7
ISBN: 978-1-4799-5267-0
pp.86-91
Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm) <14, 2014, Lake Buena Vista/Fla.>
English
Conference Paper, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
thermal optimization; Floorplanning; octree based finite element method

Abstract
During the design of 2.5D and 3D integrated systems the thermal management of the whole system is important, especially in high performance systems with combinations of processor and memory dies utilizing the Wide I/O memory interface. Because cooling solutions could be very expensive they should be considered in very early design cycles. For example, the decision if the system is implemented as a real stacked system or using an interposer strongly influences the required cooling solution. Furthermore, high performance systems with data transfer rates in the range of 100 Gbit/s to400 Gbit/s between processor and memory require an early and fast floorplan calculation to determine and optimize the heat distribution within the system (i.e., dies and package).In this paper, an appropriate floorplanner with direct access to an octree based finite element solver for the calculation of the heat distribution of the whole system is presented. Our approach allows an efficient design space exploration. The thermal simulation on system level, including heat sink and package, makes it unnecessary to manually set the boundary conditions of the chips. Thus, this approach prevents possible errors caused by this step. To illustrate the new analysis and optimization approach, it is applied to a Wide I/O 2.5D or 3D integrated system, respectively.

: http://publica.fraunhofer.de/documents/N-324026.html