Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Enriching UVM in SystemC with AMS extensions for randomization and functional coverage

: Vörtler, Thilo; Klotz, Thomas; Einwich, Karsten; Li, Yao; Wang, ZHi; Louërat, Marie- Minerve; Chaput, Jean-Paul; Pêcheux, François; Iskander, Ramy; Barnasconi, Martin

Design and Verification Conference and Exhibition Europe, DVCon 2014. CD-ROM : October 14 - 15, 2014, Munich, Germany
Munich, 2014
9 pp.
Design and Verification Conference and Exhibition Europe (DVCon) <2014, Munich>
Conference Paper
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

The Universal Verification Methodology (UVM) is a coverage driven verification approach, which has become the standard for the verification of digital systems. The framework provided by UVM makes it possible to create structured test environments, which facilitates the reuse of verification components and scenarios. However, the UVM library is only available for SystemVerilog, limiting the verification of designs at the register transfer level. Recently, UVM has been made available in SystemC/C++, shifting the focus to system-level verification including analog/mixed-signal functions by using SystemC-AMS. However, UVM itself fully relies on features built directly into the SystemVerilog language necessary for constrained randomization and functional coverage. In this paper we propose an API similar to SystemVerilog that enables randomization and coverage in UVM for SystemC. A special focus is the introduction of continuous distribution functions for the randomization of real-value data types and means to capture these real values for functional coverage. These extensions will allow the creation of coverage-based test environments in SystemC and SystemC-AMS, enabling verification of heterogeneous analog/mixed-signal systems.